c - How do memory fences work? -
I have to understand the memory fence in multicore machines. Say I have this code
core1 mov [_x], 1; Mov r1, [_y] core2 mov [_y], 1; Mov r2, [_x] Now there will be unpredictable results without the memory fence that both R1 and R2 can be 0 after the execution. In my opinion, to combat that problem, we should keep the memory fence in both the codes, because keeping it as only one will not solve the problem still. Something like this is ...
core1 mov [_x], 1; Memory_fence; Mov r1, [_y] core2 mov [_y], 1; Memory_fence; Mov r2, [_x] Is my understanding correct or am I still missing something? Let's assume that architecture is x86, besides, someone can tell me how to insert the memory fence in the C ++ code?
Fences can perform serial operations; they can perform fences (loads and reserves), i.e., execute fences No other operation can begin till, but the fences will not be completed till all previous operations. This is derived from Intel Intel by means of a little more accurate (MFNEEEE, Page 3-628, Volume 2A, Intel Instruction Reference):
This serial operation guarantees that every load And store instruction which occurs before the MFNECE directive in the sequence of the program, any load or store that comes after MFNEEEEEIECTION appears at the world level before the instruction.
- When loaded, weight instructions are considered to be visible globally and are loaded in their destination register.
It is difficult to use fences in C ++ (C +1111 fencing can be semantic, maybe someone else has information about it), it The stage and the compiler are dependent. For MS 86 by MSWC or ICC, you can call _mm_lfence , _mm_sfence & amp; To load, store and load + store fencing, _mm_mfence (note that some of these are SSE2 instructions). Note: It considers an Intel perspective, which means: An x86 (32 or 64 bit) or IA 64 processor
mov [_x], 1; Mov r1, [_y] core2 mov [_y], 1; Mov r2, [_x] Now there will be unpredictable results without the memory fence that both R1 and R2 can be 0 after the execution. In my opinion, to combat that problem, we should keep the memory fence in both the codes, because keeping it as only one will not solve the problem still. Something like this is ...
core1 mov [_x], 1; Memory_fence; Mov r1, [_y] core2 mov [_y], 1; Memory_fence; Mov r2, [_x] Is my understanding correct or am I still missing something? Let's assume that architecture is x86, besides, someone can tell me how to insert the memory fence in the C ++ code?
Fences can perform serial operations; they can perform fences (loads and reserves), i.e., execute fences No other operation can begin till, but the fences will not be completed till all previous operations. This is derived from Intel Intel by means of a little more accurate (MFNEEEE, Page 3-628, Volume 2A, Intel Instruction Reference):
This serial operation guarantees that every load And store instruction which occurs before the MFNECE directive in the sequence of the program, any load or store that comes after MFNEEEEEIECTION appears at the world level before the instruction.
- When loaded, weight instructions are considered to be visible globally and are loaded in their destination register.
It is difficult to use fences in C ++ (C +1111 fencing can be semantic, maybe someone else has information about it), it The stage and the compiler are dependent. For MS 86 by MSWC or ICC, you can call _mm_lfence , _mm_sfence & amp; To load, store and load + store fencing, _mm_mfence (note that some of these are SSE2 instructions). Note: It considers an Intel perspective, which means: An x86 (32 or 64 bit) or IA 64 processor
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